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Advanced ASIC Chip Synthesis Using Synopsys® Design Compiler™ and PrimeTime®

Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® and PrimeTime® describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted...

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Bibliographic Details
Main Author: Bhatnagar, Himanshu
Format: eBook
Language:English
Published: New York, NY Springer US 1999, 1999
Edition:1st ed. 1999
Subjects:
Computer-aided Engineering (cad, Cae) And Design
Electrical And Electronic Engineering
Electrical Engineering
Electronic Circuits
Computer-aided Engineering
Electronic Circuits And Systems
Online Access:
Collection: Springer Book Archives -2004 - Collection details see MPG.ReNa
Table of Contents:
  • 1: Asic Design Methodology
  • 1.1 Typical Design Flow
  • 1.2 Chapter Summary
  • 2: Tutorial
  • 2.1 Example Design
  • 2.2 Initial Setup
  • 2.3 Pre-Layout Steps
  • 2.4 Floorplanning and Routing
  • 2.5 Post-Layout Steps
  • 2.6 Chapter Summary
  • 3: Basic Concepts
  • 3.1 Synopsys Products
  • 3.2 Synthesis Environment
  • 3.3 Objects, Variables and Attributes
  • 3.4 Finding Design Objects
  • 3.5 Synopsys Formats
  • 3.6 Data Organization
  • 3.7 Design Entry
  • 3.8 Compiler Directives
  • 3.9 Chapter Summary
  • 4: Synopsys Technology Library
  • 4.1 Library Basics
  • 4.2 Delay Calculation
  • 4.3 What is a Good Library?
  • 4.4 Chapter Summary
  • 5: Partitioning And Coding Styles
  • 5.1 Partitioning for Synthesis
  • 5.2. What is RTL?
  • 5.3 General Guidelines
  • 5.4 Logic Inference
  • 5.5 Order Dependency
  • 5.6 Chapter Summary
  • 6: Constraining Designs
  • 6.1 Environment and Constraints
  • 6.2 Advanced Constraints
  • 6.3 Clocking Issues
  • 6.4 Putting it Together
  • 6.5 Chapter Summary
  • 7: Optimizing Designs
  • 7.1 Design Space Exploration
  • 7.2 Total Negative Slack
  • 7.3 Compilation Strategies
  • 7.4 Resolving Multiple Instances
  • 7.5 Optimization Techniques
  • 7.6 Chapter Summary
  • 8: Design For Test
  • 8.1 Types of DFT
  • 8.2 Scan Insertion
  • 8.3 DFT Guidelines
  • 8.4 Chapter Summary
  • 9: Links To Layout & Post Layout Opt
  • 9.1 Generating Netlist for Layout
  • 9.2 Layout
  • 9.3 Post-Layout Optimization
  • 9.4 Future Directions
  • 9.5 Chapter Summary
  • 10: Sdf Generation
  • 10.1 SDF File
  • 10.2 SDF File Generation
  • 10.3 Chapter Summary
  • 11; Primetime Basics
  • 11.1 Introduction
  • 11.2 Tcl Basics
  • 11.3 PrimeTime Commands
  • 11.4 Chapter Summary
  • 12: Static Timing Analysis
  • 12.1 Why Static Timing Analysis?
  • 12.2 Timing Exceptions
  • 12.3 Disabling Timing Arcs
  • 12.4 Environment and Constraints
  • 12.5 Pre-Layout
  • 12.6Post-Layout
  • 12.7 Analyzing Reports
  • 12.8 Advanced Analysis
  • 12.9 Chapter Summary

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