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131104 ||| eng |
| 020 |
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|a 9781461442745
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| 100 |
1 |
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|a Tatas, Konstantinos
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| 245 |
0 |
0 |
|a Designing 2D and 3D Network-on-Chip Architectures
|h Elektronische Ressource
|c by Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch
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| 250 |
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|a 1st ed. 2014
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| 260 |
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|a New York, NY
|b Springer New York
|c 2014, 2014
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| 300 |
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|a XIII, 265 p. 144 illus., 79 illus. in color
|b online resource
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| 505 |
0 |
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|a Part I: Network-on-Chip Design Methodology -- Network-on-Chip Technology: A Paradigm Shift -- NoC Modeling and Topology Exploration -- Communication Architecture -- Power and Thermal Effects and Management -- NoC-based System Integration -- NoC Verification and Testing -- The Spidergon STNoC -- Middleware Memory Management in NoC -- On Designing 3-D Platforms -- The SYSMANTIC NoC Design and Prototyping Framework -- Part II: Suggested Projects.- Projects on Network-on Chip
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| 653 |
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|a Electronics and Microelectronics, Instrumentation
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| 653 |
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|a Electronic circuits
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| 653 |
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|a Processor Architectures
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| 653 |
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|a Microprocessors
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| 653 |
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|a Electronics
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| 653 |
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|a Electronic Circuits and Systems
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| 653 |
|
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|a Computer architecture
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| 700 |
1 |
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|a Siozios, Kostas
|e [author]
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| 700 |
1 |
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|a Soudris, Dimitrios
|e [author]
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| 700 |
1 |
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|a Jantsch, Axel
|e [author]
|
| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
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| 989 |
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|b Springer
|a Springer eBooks 2005-
|
| 028 |
5 |
0 |
|a 10.1007/978-1-4614-4274-5
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| 856 |
4 |
0 |
|u https://doi.org/10.1007/978-1-4614-4274-5?nosfx=y
|x Verlag
|3 Volltext
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| 082 |
0 |
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|a 621.3815
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| 520 |
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|a This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty. Case studies are used to illuminate new design methodologies. · Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; · Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; · Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management
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