High Performance Embedded Architectures and Compilers : Fourth International Conference, HiPEAC 2009

This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and...

Full description

Corporate Author: SpringerLink (Online service)
Other Authors: Seznec, André (Editor), Emer, Joel (Editor), O'Boyle, Michael (Editor), Martonosi, Margaret (Editor)
Format: eBook
Published: Berlin, Heidelberg Springer Berlin Heidelberg 2009, 2009
Edition:1st ed. 2009
Series:Theoretical Computer Science and General Issues
Online Access:
Collection: Springer eBooks 2005- - Collection details see MPG.ReNa
Table of Contents:
  • Challenges on the Road to Exascale Computing
  • Keynote: Compilers in the Manycore Era
  • I Dynamic Translation and Optimisation
  • Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
  • Predictive Runtime Code Scheduling for Heterogeneous Architectures
  • Collective Optimization
  • High Speed CPU Simulation Using LTU Dynamic Binary Translation
  • II Low Level Scheduling
  • Integrated Modulo Scheduling for Clustered VLIW Architectures
  • Software Pipelining in Nested Loops with Prolog-Epilog Merging
  • A Flexible Code Compression Scheme Using Partitioned Look-Up Tables
  • III Parallelism and Resource Control
  • MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor
  • IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor
  • A Hardware Task Scheduler for Embedded Video Processing
  • Finding Stress Patterns in Microprocessor Workloads
  • IV Communication
  • An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
  • In-Network Caching for Chip Multiprocessors
  • VIII Parallel Embedded Applications
  • Parallel LDPC Decoding on the Cell/B.E. Processor
  • Parallel H.264 Decoding on an Embedded Multicore Processor
  • Hybrid Dataflow Graph Execution in the Issue Logic
  • Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
  • VII Cache Issues
  • Revisiting Cache Block Superloading