Minimizing and Exploiting Leakage in VLSI Design
In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabr...
| Main Authors: | , , |
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| Format: | eBook |
| Language: | English |
| Published: |
New York, NY
Springer US
2010, 2010
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| Edition: | 1st ed. 2010 |
| Subjects: | |
| Online Access: | |
| Collection: | Springer eBooks 2005- - Collection details see MPG.ReNa |
Table of Contents:
- Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes
- Existing Leakage Minimization Approaches
- Computing Leakage Current Distributions
- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities
- The HL Approach: A Low-Leakage ASIC Design Methodology
- Simultaneous Input Vector Control and Circuit Modification
- Optimum Reverse Body Biasing for Leakage Minimization
- I: Conclusions and Future Directions
- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design
- Exploiting Leakage: Sub-threshold Circuit Design
- Adaptive Body Biasing to Compensate for PVT Variations
- Optimum VDD for Minimum Energy
- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining
- II: Conclusions and Future Directions
- Design of a Sub-threshold BFSK Transmitter IC
- Design of the Chip
- Implementation of the Chip
- Experimental Results