Designing Reliable and Efficient Networks on Chips
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...
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| Format: | eBook |
| Language: | English |
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Dordrecht
Springer Netherlands
2009, 2009
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| Edition: | 1st ed. 2009 |
| Series: | Lecture Notes in Electrical Engineering
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| Online Access: | |
| Collection: | Springer eBooks 2005- - Collection details see MPG.ReNa |
| Summary: | Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design |
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| Physical Description: | X, 198 p online resource |
| ISBN: | 9781402097577 |